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Technical Reference

2.6 Interrupts

Table 16. Interrupts

IRQ System Resource

NMI I/O channel check

0 Reserved, interval timer

1 Reserved, keyboard buffer full

2 Reserved, cascade interrupt from slave PIC

3COM2

(Note)

4COM1

(Note)

5 LPT2 (Plug and Play option) / Audio / User available

6 Diskette drive

7LPT1

(Note)

8 Real-time clock

9 Reserved for ICH2 system management bus

10 User available

11 User available

12 Onboard mouse port (if present, else user available)

13 Reserved, math coprocessor

14 Primary IDE (if present, else user available)

15 Secondary IDE (if present, else user available)

Note: Default, but can be changed to another IRQ.

2.7 PCI Interrupt Routing Map

This section describes interrupt sharing and how the interrupt signals are connected between the

PCI bus connectors and onboard PCI devices. The PCI specification specifies how interrupts can

be shared between devices attached to the PCI bus. In most cases, the small amount of latency

added by interrupt sharing does not affect the operation or throughput of the devices. In some

special cases where maximum performance is needed from a device, a PCI device should not share

an interrupt with other PCI devices. Use the following information to avoid sharing an interrupt

with a PCI add-in card.

PCI devices are categorized as follows to specify their interrupt grouping:

• INTA: By default, all add-in cards that require only one interrupt are in this category. For

almost all cards that require more than one interrupt, the first interrupt on the card is also

classified as INTA.

• INTB: Generally, the second interrupt on add-in cards that require two or more interrupts is

classified as INTB. (This is not an absolute requirement.)

• INTC and INTD: Generally, a third interrupt on add-in cards is classified as INTC and a

fourth interrupt is classified as INTD.

1 2 ... 69 70 71 72 73 74 75 76 77 78 79 ... 152 153

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